Episode

Breaking the Memory Wall in the Age of Inference

Podcast: The Data Exchange with Ben Lorica
Published: Feb 12, 2026
Duration seconds: 2743
Processing state: processed
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Summary

Sid Sheth, CEO of D-Matrix, explains how digital in-memory computing (DIMC) overcomes the 'memory wall' bottleneck in AI inference. The discussion focuses on reducing data movement to significantly improve energy efficiency and token generation speed.

Topics

AI Inference
Digital In-Memory Computing
Hardware Accelerators
Transformer Models
Memory Wall
Data Center Infrastructure
Semiconductor Manufacturing
Edge Computing

Highlights

Main idea: The 'memory wall' occurs because moving model parameters between memory and compute consumes excessive time and energy
Practical takeaway: Digital in-memory computing (DIMC) allows matrix operations to happen directly where parameters are stored, eliminating data movement
Failure mode: Hardware startups often fail if they lack experience navigating the complex, high-stakes physical cycles of chip tape-outs
Efficiency metric: Moving from traditional architectures to DIMC can enable running 100B+ parameter models within a single rack with 5-10x better efficiency
Industry trend: The future of AI scaling depends on emerging Ethernet-based scale-up networks like Broadcom's ESun to connect servers within racks

Chapters

1:00 The Importance of Chip Industry Experience: A discussion on why successful AI hardware ventures require veterans who have navigated multiple successful chip tape-outs.
4:20 The Shift from Training to Inference: Analyzing why the hardware focus is moving from model training to the massive scale required for inference in data centers.
14:30 The Memory Wall and Data Movement: An analogy of the highway bottleneck between compute and memory, and how moving data creates a performance ceiling.
21:10 The Persistence of Matrix Math: Why fundamental matrix operations remain the core of AI hardware and how to optimize them without changing the underlying math.
24:40 Digital In-Memory Computing (DIMC): How D-Matrix uses SRAM-tier computing to process parameters in place, drastically reducing energy and latency.
42:00 Scaling via Rack-Level Interconnects: The role of Ethernet-based scale-up networks and the competition between NVLink, ESun, and UAL in connecting AI servers.
45:30 Open Standards in AI Hardware: D-Matrix's approach to embracing open software stacks like PyTorch and hardware standards like UCIe and Ethernet.